23 lines
1.0 KiB
Markdown
23 lines
1.0 KiB
Markdown
# Memory Bus Access Management
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`bitvec` allows a program to produce handles over memory that do not *logically*
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alias their bits, but *may* alias their hardware locations. This module provides
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a unified interface for memory accesses that can be specialized to handle such
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aliased and unaliased events.
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The [`BitAccess`] trait provides capabilities to access individual or clustered
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bits in memory elements through shared, maybe-aliased, references. Its
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implementations are responsible for coördinating synchronization and contention
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as needed.
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The [`BitSafe`] trait guards [`Radium`] types in order to forbid writing through
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shared-only references, and require access to an `&mut` exclusive reference for
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modification. This permits other components in the crate that do *not* have
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`BitSafe` reference guards to safely mutate a referent element that a `BitSafe`d
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reference can observe, while preventing that reference from emitting mutations
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of its own.
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[`BitAccess`]: self::BitAccess
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[`BitSafe`]: self::BitSafe
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[`Radium`]: radium::Radium
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