35 lines
1.6 KiB
Markdown
35 lines
1.6 KiB
Markdown
# Bit-Addressable Memory Regions
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This module defines the [`BitSlice`] region, which forms the primary export item
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of the crate. It is a region of memory that addresses each bit individually, and
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is analogous to the slice language item. See `BitSlice`’s documentation for
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information on its use.
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The other data structures `bitvec` offers are built atop `BitSlice`, and follow
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the development conventions outlined in this module. Because the API surface for
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`bitvec` data structures is so large, they are broken into a number of common
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submodules:
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- `slice` defines the `BitSlice` data structure, its inherent methods
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that are original to `bitvec`, as well as some free functions.
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- `slice::api` defines ports of the `impl<T> [T]` inherent blocks from
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`core::slice`.
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- `slice::iter` contains all the logic used to iterate across `BitSlices`,
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including ports of `core::slice` iterators.
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- `slice::ops` contains implementations of `core::ops` traits that power
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operator sigils.
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- `slice::traits` contains all the other trait implementations.
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- `slice::tests` contains unit tests for `BitSlice` inherent methods.
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Additionally, `slice` has a submodule unique to it: `specialization` contains
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override functions that provide faster behavior on known `BitOrder`
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implementations. Since the other data structures `Deref` to it, they do not need
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to implement bit-order specializations of their own.
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All ports of language or standard-library items have an `## Original` section in
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their documentation that links to the item they are porting, and possibly an
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`## API Differences` that explains why the `bitvec` item is not a drop-in
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replacement.
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[`BitSlice`]: self::BitSlice
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